Method for forming a plug structure and related plug structure thereof

ABSTRACT

A method for forming a plug structure by utilizing a punching through process and the related plug structure are provided. An opening is defined in a substrate, and an unwanted oxide residue is disposed on a bottom of the opening. A glue layer is subsequently formed over the substrate. Portions of the glue layer are disposed on the sidewall and bottom of the opening, and cover the oxide. Thereafter, the portion of the first glue layer disposed at the bottom of the opening is punched through until the substrate is exposed so as to remove the oxide. Next, the opening is filled with a conductive structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for forming a plug structure,and more particularly to a method of cleaning an opening by using apunching through process.

2. Description of the Prior Art

Currently, semiconductor devices are widely involved in many productsand services in our daily life. These semiconductor devices arefabricated through many processes, such as photolithography, deposition,ion implantation, or etching, to form a plurality of integrated circuit(IC) devices on a wafer. In semiconductor fabrication on a wafer, anopening with a high aspect ratio, which is defined as a ratio of thedepth to the width, is needed in some situations. The opening, such as avia hole or a contact hole, is formed in a dielectric layer and isfilled with a metallic material, such as tungsten, to form a plug.

Please refer to FIGS. 1-3. FIGS. 1-3 are schematic cross-sectionaldiagrams illustrating a method for forming a contact plug in a wafer 10according to the prior art. As shown in FIG. 1, a wafer 10 is providedfirst. The wafer 10 includes a substrate 12, a plurality ofmetal-oxide-semiconductor (MOS) devices 14 formed on the substrate 12, adielectric layer 16 covering the substrate 12, and a plurality of plugholes 18 formed in the dielectric layer 16. There are usually someunwanted oxides 50, such as native oxides, formed on the surface of theMOS devices 14. These oxides 50 will interfere the electrical connectionbetween the MOS devices 14 and the subsequently formed contact plug.

As shown in FIG. 2, in order to remove the oxides 50, an argon (Ar)cleaning process is subsequently carried out before a glue layer isformed. As the industry progresses into submicron processing techniques,a higher aspect ratio is needed for the contact plug, and it istherefore harder to completely remove all the oxides 50. As a result,the argon cleaning process should be enhanced, or the process time ofthe argon cleaning process should be extended to clean the bottom oxides50. However, when the argon cleaning process is enhanced, or the processtime of the argon cleaning process is extended, a portion of thedielectric layer 16 positioned around the top corner of the plug hole 18might be over-rounded. More the argon cleaning process is performed,more seriously the top corner of the plug hole 18 is over-rounded.

As shown in FIG. 3, a titanium layer 22 is afterward formed over thedielectric layer 16 by a physical vapor deposition (PVD) process, atitanium nitride layer 24 is next formed over the titanium layer 22 by achemical vapor deposition (CVD) process, and a tungsten layer 26 isformed over the wafer 10 to fill the plug hole 18. Thereafter, achemical mechanical polishing (CMP) process is performed to removeexcessive parts of the tungsten layer 26, excessive parts of thetitanium nitride layer 24, and excessive parts of the titanium layer 22,so as to form contact plugs 28 in the dielectric layer 16. The titaniumlayer 22 or the titanium nitride layer 24 functions as a glue layer or abarrier layer around the contact plugs 28.

Because the top corner of the plug hole 18 is over-rounded, a barrierbridge problem 30 is caused between contact plugs 28, as shown in FIG.3, especially when the critical dimension (CD) becomes smaller. Thetitanium layer 22 or the titanium nitride layer 24 electrically connectstwo independent contact plugs 28 with each other, and causes a shortcircuit in the wafer 10. Therefore, the fabricated products fail inperformance.

In order to prevent the barrier bridge problem 30 and remove the oxides50, a F-base cleaning process is carried out instead of the argoncleaning process, as shown in FIG. 4. However, the F-base selectivitywith SiO₂ and SiN is poor, so it is easy to cause the CD of the contactplug 28 to be enlarged, especially at the SiN spacer or a SiN contactetch stop layer (CESL). It is easy to widen the contact plug 28 to reachthe poly-gate of the MOS device 14, and causes a short circuit betweenthe contact plug 28 and the poly-gate.

The existence of oxides reduces the device performance, and the shortcircuit even causes a failure of the device. Accordingly, it is desiredto provide a cleaning method that does not deform the opening.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide amethod for cleaning an opening and the related plug structure so thatthe formed product has a great performance.

It is an objective of the present invention to provide a method forforming a plug structure. First, a substrate is provided. The substratehas a dielectric layer, an opening defined in the dielectric layer.Subsequently, a first glue layer is formed over the substrate. The firstglue layer is disposed at the bottom and sidewall of the opening. Next,a portion of the first glue layer disposed at the bottom of the openingis punched through until the substrate is exposed. Thereafter, theopening is filled with a conductive structure.

In accordance with another aspect of the present invention, a plugstructure is provided. The plug structure includes a substrate, amaterial layer disposed on the substrate, an opening formed in thematerial layer, a glue layer covering a sidewall of the opening, abarrier layer covering a surface of the glue layer, and a plug fillingthe opening.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings:

FIGS. 1-3 are schematic cross-sectional diagrams illustrating a methodfor forming a contact plug in a wafer according to the prior art;

FIG. 4 is a schematic cross-sectional diagram illustrating anothermethod for forming a contact plug in a wafer according to the prior art;

FIGS. 5-9 are schematic cross-sectional diagrams illustrating a methodfor forming a plug structure according to a first preferred embodimentof the invention;

FIG. 10 is a schematic cross-sectional diagram illustrating a method forforming a plug structure according to a second preferred embodiment ofthe invention;

FIGS. 11-12 are schematic cross-sectional diagrams illustrating a methodfor forming a plug structure according to a third preferred embodimentof the invention;

FIG. 13 is a schematic cross-sectional diagram illustrating a method forforming a plug structure according to a fourth preferred embodiment ofthe invention;

FIGS. 14-17 are schematic cross-sectional diagrams illustrating a methodfor forming a plug structure according to a fifth preferred embodimentof the invention;

FIGS. 18-20 are schematic cross-sectional diagrams illustrating a methodfor forming a plug structure according to a sixth preferred embodimentof the invention;

FIG. 21 is a schematic cross-sectional diagram illustrating a method forforming a plug structure according to a seventh preferred embodiment ofthe invention;

FIG. 22 is a schematic cross-sectional diagram illustrating a method forforming a plug structure according to an eighth preferred embodiment ofthe invention; and

FIGS. 23 is a schematic cross-sectional diagram illustrating a methodfor forming a plug structure according to a ninth preferred embodimentof the invention.

DETAILED DESCRIPTION

The method is suitable for cleaning any kind of opening in asemiconductor wafer, such as a via hole, a contact hole, a trench, or adamascene opening.

Please refer to FIGS. 5-9. FIGS. 5-9 are schematic cross-sectionaldiagrams illustrating a method for forming a plug structure according toa first preferred embodiment of the invention, where like numbernumerals designate similar or the same parts, regions or elements. It isto be understood that the drawings are not drawn to scale and are servedonly for illustration purposes. It is to be understood that some detailsabout etch stop layers, horizontal interconnects, advanced structures,such as dual damascene structures, lithographic and etching processesrelating to the present invention method are known in the art and thusnot explicitly shown in the drawings. As shown in FIG. 5, a wafer 110 isprovided first. The wafer 110 comprises a substrate 112, a MOS device114 formed on the substrate 112, and a dielectric layer 116 covering thesubstrate 112. An opening 118 exposing one corresponding conductingregion 104 of the MOS device 114 can be formed in the dielectric layer116 by, for example, photolithography and etching. The opening 118 canbe a high aspect ratio opening, and the width of the opening 118 isrelative small to the depth. For example, the opening 118 is a contacthole in this embodiment.

There are usually some unwanted oxides 50, such as native oxides, formedon the surface of the MOS device 114. For instance, the oxides 50 mightbe formed on the conducting regions 104 of the MOS device 114. Theseoxides 50 may degrade the electrical connection between the MOS device114 and the subsequently formed contact plug in the opening 118. Inaddition, residues (not shown in the drawing) might also formed at thebottom of the opening 118 during an etching process of forming theopening 118, where the residues usually contains high-molecule polymerswith carbon, silicon, nitrogen, fluorine, titanium, or other impurities.

The wafer 110 can also be taken as a semiconductor substrate, and canfurther include more devices or components (not shown in the drawing)therein. The substrate 112 can be made from semiconductor materials,such as a silicon substrate, a silicon-containing substrate, or asilicon-on-insulator (SOI). The conducting regions 104 of the MOS device114 can contain salicide, such as nickel silicide (NiSi), for reducingthe contact resistance between the MOS device 114 and thefollowing-formed plugs. It should be noted that the MOS device 114 couldbe replaced with any component or device, such as a diode, a capacitor,a resistor, or even a metallic structure, that should be electricallyconnected to a plug or to a trench. The dielectric layer 116 is usuallysandwiched between one metal layer on the top and the substrate 112 atthe bottom, or between two metal layers. The dielectric layer 116 cancontain lower dielectric constant (low-k) materials, such as a silicon-containing layer including fluorinated silicate glass (FSG) or acarbon-containing layer including carbon-doped oxide (CDO). In otherembodiment, the dielectric layer 116 can be replaced by other materiallayers.

As shown in FIG. 6, a glue layer 122 is substantially formed over wafer110, and a portion of the glue layer 122 can be disposed at the bottomand sidewall of the opening 118. The glue layer 122 can be applied toprotect the structure of the opening 118, and to improve the adhesionbetween the dielectric layer 116 and the subsequently formed metal plug.Accordingly, the glue layer 122 can include metal materials, such astitanium, tantalum, or tungsten. For example, the glue layer 122includes a titanium layer formed by a physical vapor deposition processin this embodiment.

As shown in FIG. 7, a punching through process is performed. The portionof the glue layer 122 disposed at the bottoms of the openings 118 ispunched through until the MOS device 114 is exposed so as to remove theunwanted oxide 50. The portion of the glue layer 122 disposed at thebottoms of the openings 118 can be punched through by using ananisotropic etching process, such as a radio-frequency (RF) sputteringprocess. The RF sputtering process includes a gas or metal, such asnitrogen gas, flushed into a reaction chamber, and a RF power sourceused to ionize the gas into ions. The wafer 110 is applied with avoltage to produce electric field, which energizes ions by acceleratingions in order to bombard the wafer 110. Accordingly, the unwanted oxide50 and the portion of the glue layer 122 disposed at the bottom of theopening 118 are removed.

An opening having overhang structure may degrade the step coverageperformance for the subsequent process for a formation of a plug. If theopening 118 has an overhang structure on each upper corner of theopening 118, the overhang structure can also be remove by utilizing theabove-mentioned punching through process. The avoidance of the overhangstructure of the glue layer on the upper corners of the opening canimprove the step coverage performance.

It deserves to be mentioned that other portions of the glue layer 122disposed on the surface of the dielectric layer 116 might also beremoved in the above-mentioned punching through process. For example,the top surface of the dielectric layer 116 outside the opening 118might be exposed in this embodiment after the punching through process.In other embodiments, portions of the glue layer 122 disposed on thesidewalls of the openings 118 might be removed, or portions of the gluelayer 122 disposed on the top surface of the dielectric layer 116 mightnot be removed. The removed portions and the remained portions of theglue layer 122 can be modified by adjusting parameters of the punchingthrough process or by a patterned hard mask.

As shown in FIG. 8, a barrier layer 124 is next formed over the wafer110, and a conductive material 126 is thereafter formed to fill theopening 118. The barrier layer 124 can cover the bottom of the opening118 and the surface of the glue layer 122. The barrier layer 124 can beapplied to improve the ohmic contact between the conducting regions 104of the MOS device 114 and the conductive material 126. Accordingly, thebarrier layer 124 can include refractory or noble metal or compound,such as titanium nitride, tantalum nitride, tungsten nitride, or theircombination. For example, the barrier layer 124 can include a titaniumnitride layer formed by a chemical vapor deposition (CVD) process inthis embodiment. The conductive material 126 can be any material havinga high conductivity, such as tungsten, copper, aluminum, other metals ortheir alloy. For instance, the conductive material 126 can includetungsten formed by a deposition process in this embodiment.

Afterward, as shown in FIG. 9, a planarization process, such as achemical mechanical polishing process, is performed to remove excessiveportions of the conductive material 126, and excessive portions of thebarrier layer 124, so as to form a plurality of plug structures 128 inthe dielectric layer 116. The remained conductive material 126 thereforebecomes a conductive structure. A plug structure is usually applied tointerconnect two conductive components for an interconnection betweendevices. In this embodiment, the plug structures 128 function as contactplugs to electrically connect the lower MOS devices 114 with the uppermetal layer or with other devices. In practice, the punching throughprocess can be applied to any fabrication, in which an opening should becleaned. For example, the present invention can be applied to afabrication of a via plug, a fabrication of a contact plug, afabrication of a damascene structure, or even a fabrication of a shallowtrench isolation.

It is worthy of note that the fabrication of the barrier layer 124 canbe eliminated in some embodiments. Please refer to FIG. 10, which is aschematic cross-sectional diagram illustrating a method for forming aplug structure according to a second preferred embodiment of theinvention. As shown in FIG. 10, the fabrication of the barrier layer 124can be eliminated if the conductive material 126 is formed by a chemicalvapor deposition process, where tungsten hexafluoride (WF₆), tungstenchloride (WCl₆) or tungsten trioxide (WO₃) is utilized as the tungstensource. In addition, if the conductive material 126 is formed in aco-reactant system, where organometallic precursors, such as tungstenhexacarbonyl (W(CO)₆), is employed, or the conductive material 126 isformed by a metal organic chemical vapor deposition (MOCVD) process,where Cl₄(CH₃CN)W(NPr) is utilized as precursor, the fabrication of thebarrier layer 124 can be eliminated.

In other embodiments, another glue layer can be formed over the wafer110 after the glue layer 122 is punched through. Please refer to FIGS.11-12, which are schematic cross-sectional diagrams illustrating amethod for forming a plug structure according to a third preferredembodiment of the invention, where like number numerals designatesimilar or the same parts, regions or elements. In this embodiment, awafer 110 having a structure similar to the wafer 110 shown in FIG. 5can be first provided. Subsequently, a glue layer 122 can be formed overthe wafer 110, and a punching through process can be performed to removethe portion of glue layer 122 and the oxide 50 positioned at the bottomof the opening 118 according to the steps shown in FIG. 6 and FIG. 7.

Thereafter, as shown in FIG. 11, another glue layer 132 can be formedover the wafer 110, a barrier layer 124 is next formed on the glue layer132, and a conductive material 126 is next formed to fill the opening118. A portion of the glue layer 132 is disposed at the bottom of theopening 118, and covers the surface of the glue layer 122. The gluelayer 132 can include metal materials, such as titanium, tantalum, ortungsten. For example, the glue layer 132 can include a titanium layerformed by a physical vapor deposition process.

Afterward, as shown in FIG. 12, a planarization process is performed toremove excessive portions of the conductive material 126, excessiveportions of the barrier layer 124, and excessive portions of the gluelayer 132, so as to form a plurality of plug structures 228 in thedielectric layer 116. In this embodiment, the glue layer 132 can beapplied for improving the adhesion between the MOS devices 114 and thesubsequently formed metal plug.

The fabrication of the barrier layer 124 shown in FIG. 12 can also beeliminated. Please refer to FIG. 13, which is a schematiccross-sectional diagram illustrating a method for forming a plugstructure according to a fourth preferred embodiment of the invention.As shown in FIG. 13, the fabrication of the barrier layer 124 can beeliminated, so the conductive material 126 covers the surface of theglue layer 132 and contacts the MOS devices 114.

Portions of the barrier layer 124 shown in FIG. 8 can also be punchedthrough. Please refer to FIGS. 14-17, which are schematiccross-sectional diagrams illustrating a method for forming a plugstructure according to a fifth preferred embodiment of the invention,where like number numerals designate similar or the same parts, regionsor elements. As shown in FIG. 14, a wafer 110, which has undergone thesteps shown in FIGS. 5-8, is provided, and thus has a structure as sameas the wafer 110 shown in FIG. 8.

Subsequently, as shown in FIG. 15, portions of the barrier layer 124disposed at the bottoms of the openings 118 is punched through until theMOS device 114 is exposed, where the glue layer 122 can be punchedthrough by using an anisotropic etching process, such as aradio-frequency sputtering process. If the opening 118 has an overhangstructure of the barrier layer 124 on each upper corner of the opening118, the overhang structure can also be removed during this punchingthrough process.

Afterward, as shown in FIG. 16, another barrier layer 134 is formed onthe barrier layer 124, and a conductive material 126 is next formed tofill the opening 118. Next, as shown in FIG. 17, a planarization processis performed to remove excessive portions of the conductive material 126and excessive portions of the barrier layer 134 so as to form aplurality of plug structures 528 in the dielectric layer 116.

Furthermore, portions of the barrier layer 124 can be punched throughimmediately after the glue layer 122 is punched through in otherembodiments. Please refer to FIGS. 18-20, which are schematiccross-sectional diagrams illustrating a method for forming a plugstructure according to a sixth preferred embodiment of the invention. Asshown in FIG. 18, a wafer 110, which has undergone the steps shown inFIGS. 5-6, is provided, and a barrier layer 124 is next formed over thewafer 110. The glue layer 122 covers the oxides 50, and the barrierlayer 124 can cover the surface of the glue layer 122.

Subsequently, as shown in FIG. 19, portions of the barrier layer 124 andportions of the glue layer 122 disposed at the bottoms of the openings118 are punched through until the MOS device 114 is exposed, where thebarrier layer 124 and the glue layer 122 are punched through by using ananisotropic etching process. Afterward, as shown in FIG. 20, anotherbarrier layer 134 is formed on the barrier layer 124, a conductivematerial 126 is next formed to fill the opening 118, and a planarizationprocess is performed to remove excessive portions of the conductivematerial 126 and excessive portions of the barrier layer 134 so as toform a plurality of plug structures 628 in the dielectric layer 116.

In other embodiments, the fabrication of the barrier layer 134 shown inFIG. 16 or FIG. 20 can also be eliminated. Please refer to FIG. 21 andFIG. 22. FIG. 21 is a schematic cross-sectional diagram illustrating amethod for forming a plug structure according to a seventh preferredembodiment of the invention, and FIG. 22 is a schematic cross-sectionaldiagram illustrating a method for forming a plug structure according toan eighth preferred embodiment of the invention. As shown in FIG. 21,the fabrication of the barrier layer 134 can be eliminated, so theconductive material 126 covers the surface of the barrier layer 124, andcontacts the MOS devices 114.

In the above-mentioned embodiments, tungsten process is taken asexamples to specifically illustrate the cleaning method of the presentinvention. In other embodiments, the utilized materials, the patterns ofthe openings, or the devices positioned under the plugs can be change ormodified. For example, the present invention can be applied to a copperprocess. Please refer to FIGS. 23, which is a schematic cross-sectionaldiagram illustrating a method for forming a plug structure according toa ninth preferred embodiment of the invention, where like numbernumerals designate similar or the same parts, regions or elements. Themain differences between the first preferred embodiment and the ninthpreferred embodiment are the semiconductor devices positioned under theplugs and the materials of the glue layer, the barrier layer, and theconductive material.

As shown in FIG. 23, the MOS devices 114 are replaced with metallicstructures 214, the glue layer 122 is replaced with a glue layer 222,the barrier layer 124 is replaced with a barrier layer 224, and theconductive material contains copper. In this embodiment, the glue layer222 includes a tantalum layer, and the barrier layer 224 can include atantalum nitride layer in accordance with a copper process. The gluelayer 222 and the barrier layer 224 can further prevent the diffusion ofcopper into the dielectric layer 116, which would short out thedielectric between neighboring via, or the diffusion of oxygen from thedielectric 116 into the metallic structures 214, which reduces theconductivity of the plug. In the case of copper process, the fillingprocess typically includes a physical vapor deposition or sputteringdeposition of the copper seed layer 238 followed by an electrochemicalplating (ECP) of copper into the openings 118. Therefore, a plurality ofplug structures 928 is formed, where each opening 118 is filled with aconductive structure. Each conductive structure includes a seed layer238 covering a surface of the barrier layer, and a conductive material236 filling the opening 118.

In addition, it should be noted that a pre-cleaning process could befurther performed before the deposition of the glue layer 122 in theabove-mentioned embodiments. For example, an Ar pre-cleaning process oran F-base pre-cleaning process can be performed to remove portions ofthe oxides. In order to protect the structures of the openings, the Arpre-cleaning process must be soft and delicate, and should not beperformed for a long time, in which most of the oxides remain in theopenings.

Since the present invention utilizes a punch through process to removethe unwanted oxides disposed at the bottom of the opening, there aresome advantages for the present invention as following listed. First,the method can contain no Ar cleaning process nor F-base cleaningprocess that deforms the structure of the opening. Therefore, thecontact profile of the plug structure is improved, and a short circuitbetween two plugs, and a short circuit between the plug and the lowerdevice can be avoided. Subsequently, the unwanted oxides are easily andeffectively removed, so the contact resistance between the plug and thelower device can be decreased. Furthermore, the step coverage for theglue layer and the step coverage for the barrier layer are also improveddue to the punch through process. As a result, the device performancecan be increased as desired by an IC design.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention.

1. A method for forming a plug structure, the method comprising:providing a substrate, the substrate comprising a dielectric layer, anopening defined in the dielectric layer forming a first glue layer overthe substrate, the first glue layer being disposed on a sidewall and thebottom of the opening; punching through a portion of the first gluelayer disposed at the bottom of the opening until the substrate isexposed; and filling the opening with a conductive structure.
 2. Themethod of claim 1, further comprising a step of forming a second gluelayer over the substrate after the first glue layer is punched through.3. The method of claim 2, further comprising a step of forming a barrierlayer over the substrate after the second glue layer is formed.
 4. Themethod of claim 1, further comprising a step of forming a barrier layerover the substrate after the first glue layer is punched through.
 5. Themethod of claim 4, further comprising a step of punching through aportion of the barrier layer disposed at the bottom of the opening afterthe barrier layer is formed.
 6. The method of claim 1, furthercomprising a step of forming a barrier layer over the substrate beforethe first glue layer is punched through.
 7. The method of claim 6,wherein the step of punching through the portion of the first glue layeralso punches through a portion of the barrier layer disposed at thebottom of the opening.
 8. The method of claim 1, further comprising astep of performing a pre-cleaning process before the first glue layer isformed.
 9. The method of claim 8, wherein the pre-cleaning processcomprises an argon (Ar) or F-base pre-cleaning process.
 10. The methodof claim 1, wherein the step of punching through the portion of thefirst glue layer is performed by using an anisotropic etching process.11. The method of claim 10, wherein the anisotropic etching processcomprises a radio-frequency (RF) sputtering process.
 12. The method ofclaim 1, wherein the first glue layer comprises titanium (Ti), tantalum(Ta), or tungsten (W).
 13. The method of claim 3, wherein the barrierlayer comprises titanium nitride, tantalum nitride, or tungsten nitride.14. The method of claim 1, wherein the substrate further comprises asemiconductor device, and the semiconductor device comprises aconducting region; wherein the conducting region comprises nickelsilicide (NiSi), and the conductive structure comprises tungsten.
 15. Aplug structure, comprising: a substrate; a dielectric layer disposed onthe substrate; an opening defined in the dielectric layer; a glue layercovering a sidewall of the opening; a barrier layer covering a surfaceof the glue layer; and a conductive structure filling the opening. 16.The plug structure of claim 15, wherein the barrier layer covers aportion of the substrate at a bottom of the opening.
 17. The plugstructure of claim 15, wherein the conductive structure contacts aportion of the substrate at a bottom of the opening.
 18. The plugstructure of claim 15, wherein the conductive structure comprises a seedlayer covering a surface of the barrier layer, and a conductive materialfilling the opening; wherein the seed layer and the conductive materialcomprise copper.
 19. The plug structure of claim 16, wherein thesubstrate comprises a semiconductor device, and the semiconductor devicecomprises a conducting region; wherein the conducting region comprisesnickel silicide, and the conductive structure comprises tungsten. 20.The plug structure of claim 15, wherein the glue layer comprisestitanium, tantalum, or tungsten, and the barrier layer comprisestitanium nitride, tantalum nitride, or tungsten nitride.